| 摘要 |
PURPOSE:To improve the degree of integration by forming a connecting hole shaped in a self-alignment manner to a gate electrode by a third insulating film and forming a wiring connected to a source region or a drain region in a field-effect transistor through the connecting hole onto a second insulating film. CONSTITUTION:One semiconductor region 13 of an MISFET Qs for a memory cell is connected electricity to a data line 17A through connecting holes 15 and 16. The connecting hole 15 is constituted surrounded by an insulating film 14A formed in a self-alignment manner to a gate electrode 11A on the connected side with the data line 17A in one side section of the gate electrode 11A and a field insulating film 2, and organized in the self-alignment manner even to approximately the field insulating film 2. The isolation voltage of the gate electrode 11A and the data line 17A is ensured by an insulating film 12 on the gate electrode 11A and the insulating film 14A on a side section. Accordingly, an area required for connecting one semiconductor region 13 in the MISFET Qs for the memory cell and the data line 17A can be reduced, thus improving the degree of integration of a DRAM. |
