Alu for a bit slice processor with multiplexed bypass path.

摘要

A bit slice ALU for a bit slice processing system includes an ALU (36) which has data input from a register file (50) onto input buses (40) and (38). The output of the ALU (36) is input to a multiplexer (86) which has the other input thereof connected to a bypass bus (71) for bypassing data around the ALU (36). The multiplexer (86) is controlled by a decode logic circuit (108) for selecting the output of the ALU (36) or the bypass bus (71). A decision logic circuit (90) is provided for determining status information of the data to be processed and outputting a feedback signal on a line (112) to the decode logic circuit (108) for the multiplexer (86). The decision logic circuit (90) operates in parallel with the processing operation of the ALU (36) such that either the processed data can be selected or the bypassed data on the bus (71) can be selected. This significantly increases the speed of the processing system for select functions.