| 摘要 |
PURPOSE:To speed-up a readout by raising rapidly a voltage between a gate and a source connected to a word line, by connecting and operating the source of a MOSFET within a memory cell to a data line. CONSTITUTION:Through the use of a pre-charge signal phiP, a data line D0, the inverse of D0, a common data line DC, and the inverse of DC, are pre-charged on a power source voltage VCC. Next, an address signal is inputted to a decoder 20, and word lines W0-W63, the inverse of W0-W63, a dummy word line WD, and the inverse of WD are selected, and their potentials are discharged. And P-channel MOSs Q4 and Q6, when the voltages between their gates and sources rise larger than a threshold level, enter on-states, and the potential of the data line is lowered corresponding to the terminal voltage of a capacitance C4. Furthermore, when the word line continues to discharge, the conductance of the MOSQ4 is increased, and the readout of the data can be performed at high speed.
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