发明名称 Two stage decoder circuit using threshold logic to decode high-order bits and diode-matrix logic to decode low-order bits
摘要 A two-stage decoder circuit includes a first-stage decoder circuit, for decoding upper bits of an input signal, and a second-stage decoder circuit, which is activated by receiving a selected output signal of the first-stage decoder circuit and which decodes lower bits of the input signal. The first-stage decoder circuit is formed by a threshold-operation type logic circuit which carries out selection or non-selection by comparing the input signal with a predetermined threshold level, and the second-stage decoder circuit is formed by a diode-matrix circuit.
申请公布号 US4697104(A) 申请公布日期 1987.09.29
申请号 US19850737464 申请日期 1985.05.24
申请人 FUJITSU LIMITED 发明人 OKAJIMA, YOSHINORI
分类号 G11C11/41;G11C8/10;H01L21/82;H03M7/22;(IPC1-7):H03K19/086;H03K19/084 主分类号 G11C11/41
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