发明名称
摘要 PURPOSE:To perform high speed of a semiconductor device by forming different electrode materials of work functions at the side facing the element region of the first and second gate electrode, thereby shallowly forming the threshold voltages of N-channel and P-channel MOS transistors. CONSTITUTION:P type well region 2 and N type polycrystalline silicon patterns 51, 52 are formed on an N type silicon substrate 1, and ions are implanted selectively to form an arsenic ion implanted layer 7 and a boron ion implanted layer 9. The pattern 52 is etched to the thickness of approx. half, an Mo film 11 is deposited and heat treated. MoSi2 films 121, 122 are formed, the layers 7, 9 are activated to form N<+> type source and drain regions 13, 14 and P<+> type source and drain regions 15, 16, and an N-channel transistor having the first gate electrode of 2-layer structure of the pattern 51 and the film 121, and a P-channel transistor having the second gate electrode formed of the film 122 are formed.
申请公布号 JPS6245708(B2) 申请公布日期 1987.09.28
申请号 JP19830000840 申请日期 1983.01.07
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 KOBAYASHI HIROSHI;MIZUTANI YOSHIHISA
分类号 H01L27/092;H01L21/8238;H01L29/78;H01L29/786 主分类号 H01L27/092
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