| 摘要 |
PURPOSE:To reduce the source/drain region resistance as well as the gate electrode wiring resistance by a method wherein a silicide layer is formed on the surface of source/drain regions to laminate metallic layer through the intermediary of a tunnel insulating film. CONSTITUTION:A gate insulating film 4 is formed on a silicon substrate 1 and then a polysilicon layer pattern 5 forming part of a gate electrode wiring is formed. First, low concentration source/drain N-type layers 2 are formed by ion implantation and then an insulating film 8 is formed on the sidewall parts only of pattern 5. Later, the source/drain N-type layers 2 are implanted with ions to form high concentration source drain region 2. Second, the substrate 1 is heated to form a tunnel insulating film 6 comprising silicide 3 and Ta oxide film. Finally, a metallic layer 7 as a gate electrode pattern is formed further to form interlayer insulating films 9 and Al electrode wiring 10.
|
