| 摘要 |
PURPOSE:To facilitate one chip LSI by shifting sequentially the adjusting step at every communication period so as to bring the peak level of a reception signal within both extremes when the level is at the outside of the upper/lower limits thereby simplifying the titled circuit. CONSTITUTION:The peak level of the reception signal IN is compared with upper and lower threshold levels at comparators 3, 4 respectively and the result is sent to a discrimination circuit 3. The discrimination circuit 3 outputs sequentially a signal representing when the peak level is at the outside of each threshold level and within both the threshold levels. When a memory device M receives reception timing information RT at the head of a reception R at each communication period TP, the device M stores tentatively a signal in the circuit 3. In receiving the sending timing information at the head of a transmission S in succession to the reception R, an up-down counter U/D 3 shifts the gain adjusting step to the gain increasing direction by one step when the up-signal U of the device M is at H and shifts by one step in the gain decreasing direction when the down-signal D is at H level thereby revising the gain for the reception R. Thus, the signal IN is locked in the region of each threshold level.
|
