发明名称 CONTROL SYSTEM FOR ELECTRONIC COMPUTER
摘要 PURPOSE:To surely attain a break even in an overlay, etc. by carrying out the comparison between a designated address and an executed address as well as between the designated data and the contents of the executed address. CONSTITUTION:A register 36 stores a break address and a register 37 stores data on the break address respectively. Then the break address is compared with an instruction counter 33 by a comparator 38. While the data on the break address is compared an instruction register 34 by a comparator 39. An AND gate 40 detects that coincidence is obtained between results of both comparators 38 and 39 and transmits this information to a timing control part 41 to perform control for execution of a prescribed break point action. Thus it is possible to detect a desired break point even in such a case where many different data are overlaid on the same memory address.
申请公布号 JPS62217332(A) 申请公布日期 1987.09.24
申请号 JP19860061408 申请日期 1986.03.18
申请人 NEC CORP 发明人 TSUCHIDA TOMOKO
分类号 G06F11/28 主分类号 G06F11/28
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