| 摘要 |
PURPOSE:To read a data independently of an activation permissible time by latching the read data of a memory cell to a column sense amplifier and disconnecting the column sense amplifier and a bit line after the latch. CONSTITUTION:A column sense amplifier CSA is arranged to bit line pair BL, the inverse of BL and gates Q7, Q8 are inserted to disconnect the bit line pair BL, the inverse of BL and the amplifier CSA. In selecting a word line, the data of each memory cell belonging to the selected word line comes to each bit line, the data is fetched in the amplifier CSA by opening the gates Q7, Q8 and then (at refresh, etc.,), the gates Q7, Q8 are closed. Thus, other word line is selected to activate the amplifier CSA for refresh. Since the read data is latched in the amplifier CSA, the data of each bit line is read one after another via data buses DB, the inverse of DB by using a column decoder CD to open gates Q5, Q6,... one after another.
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