发明名称 FORMATION OF RECESSION IN SEMICONDUCTOR WAFER
摘要 PURPOSE:To enable recession to be formed in accurate depth by a method wherein a thin film comprising a material different from Si is formed on the monitor part on an Si substrate to epitaxially grow an Si layer in specified thickness on the Si substrate including the thin film and then the monitor part is etched to form recessions. CONSTITUTION:A thin film 2 for detecting etching terminal is formed on an Si substrate 1. Later, an Si epitaxial growing layer 3 in specified thickness is formed on the Si substrate 1 using Si vapor growing technology. Next, an etching mask with etching holes are formed on the parts directly opposing to the Si substrate 1 while the other etching hole 5 for monitor etching is formed on the part above the thin film layer 2. Furthermore, anisotropic etching process of Si vapor growing layer 3 such as reactive ion etching etc. is performed. At this time, a terminal detector such as a mass analyzer or a spectroscopic analyzer can be used so that the signal intensity at the etching time may be changed to detect the etching terminal. Through these procedures, the recessions in the depth around the thickness of Si epitaxial growing layer 3 can be formed and evaluated assuming the etching time as an unit terminal detecting time.
申请公布号 JPS62214622(A) 申请公布日期 1987.09.21
申请号 JP19860057461 申请日期 1986.03.14
申请人 MITSUBISHI ELECTRIC CORP 发明人 TOBINAGA MINETO
分类号 H01L21/302;H01L21/3065 主分类号 H01L21/302
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