发明名称 WRONG FREQUENCY CLOCK DETECTING CIRCUIT
摘要 PURPOSE:To simplify a wrong frequency clock detecting circuit by providing the 1st and the 2nd FFs which are set with the outputs of the 1st and the 2nd monostable multivibrator and an alarm means which is driven with the positive logic output of either of the 1st and the 2nd FFs and the negative logic output of the other. CONSTITUTION:An initial state is entered with a switch 5 on and it is checked whether or not the frequency of an input clock to be detected is normal with the switch 5 off by looking at the on-off state of an LED 8. When the frequency is equal to a normal frequency, the output of a monostable multivibrator 1 stays at H and the output of a monostable multivibrator 2 is turned on and off repeatedly; and the outputs of the FFs 3 and 4 are at L and the LED 8 turns off. When the frequency is lower than the normal frequency, the outputs of the monostable multivibrators 1 and 2 are both turned on and off repeatedly,, the outputs of the FFs 3 and 4 are at H and L, and the LED 8 illuminates. Then when the frequency is higher than the normal frequency, on the other hand, the outputs of the monostable multivibrators 1 and 2 stay at H, the outputs of the FFs 3 and 4 are at L and H, and the LED 8 illuminates. Thus, it is judged whether or not the frequency is normal from the on-off state of the LED 8.
申请公布号 JPS62211564(A) 申请公布日期 1987.09.17
申请号 JP19860053902 申请日期 1986.03.12
申请人 NEC CORP 发明人 OTSUKA HIROICHI
分类号 H03K5/19;G01R23/15;G06F1/04;H03K5/153;H03K5/26 主分类号 H03K5/19
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