发明名称 INSTRUCTION SEQUENCER BRANCH MECHANISM
摘要 A special-purpose, microprogrammed digital subsystem sequences through stored lists of microinstructions to produce various control signals. In response to address signals provided by an address generator, the microinstructions are accessed in pairs: A primary microinstruction and a branch or target microinstruction. For the most part, only the primary microinstruction is decoded and executed. However, certain of the ones of primary microinstructions are of the type that require a decision to be made, and the microinstruction stream branches to one of two choices depending upon the outcome of the decision. The target microinstruction forms the first microinstruction of one of the available microinstruction branches, and, if this branch is taken, is executed in parallel with the branch to avoid time penalties. An additional aspect of the invention is that the address generator, which provides address signals to a memory that stores the microinstructions, is capable of functioning as a timer circuit.
申请公布号 AU6979087(A) 申请公布日期 1987.09.17
申请号 AU19870069790 申请日期 1987.03.06
申请人 TANDEM COMPUTERS INC. 发明人 WILLIAM T. FULLER
分类号 G06F9/22;G06F9/26;G06F9/28;G06F9/38;G06F11/30 主分类号 G06F9/22
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