Adaptive digital filter

摘要

A digital filter comprises a plurality of delay stages 41 such as shift register stages through which an input x(t) is fed. Each of a plurality of individually addressable random access memories 42 is addressed by the output of one of the delay stages and the output from the RAMs 42 are combined. An error signal adapts the values stored within the RAMs. The filter may also be extended such that each RAM receives an address input from more than one delay stage.