发明名称 VERTICAL SYNCHRONIZING SEPARATOR CIRCUIT
摘要 PURPOSE:To obtain a vertical synchronizing signal free from the inflence of noises by providing a pulse generating circuit which generates a pulse whose width is wider than that of a horizontal synchronizing signal but narrower than that of the vertical synchronizing width of a vertical synchronizing cycle, and providing a resistor which reads a composite synchronizing signal at the rising of an output pulse from said pulse generating circuit. CONSTITUTION:When there is a noise N in the composite synchronizing signal, a monostable multivibrator circuit 1 generates a pulse of a width t2 at a point (g) which is the rising point of the pulse due to the noise but not the trailing edge of the composite synchronizing signal. Accordingly, the register circuit 2 is made read the point (i) of the composite synchronizing signal by the rising point (h) of said pulse of the width t2 triggered by the noise. However, at this point of reading, the influence of the noise (d) is already eliminated from the point (i), hence the circuit 2 is not subjected to the influence of noise. In such a way, a vertical synchronizing signal free from the influence of noise is obtained.
申请公布号 JPS62207071(A) 申请公布日期 1987.09.11
申请号 JP19860048434 申请日期 1986.03.07
申请人 NEC CORP 发明人 SANO YASUSHI
分类号 H04N5/10 主分类号 H04N5/10
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