| 摘要 |
PURPOSE:To execute wiring processing in compliance with the wiring length instructed by a logic designer at a high speed by changing dynamically the candidate of unwired sections at each progress of wiring. CONSTITUTION:With respect to all wiring sections, within the range of designated wire length, the wiring candidate of <=1 candidate and the least candidate number from the listed-up candidate table 21 and deciding the wire path are provided and in deciding one wire path, with respect to all unwired sections, the candidates of 2 VIA or below are listed up again to revise the table 21. Since the candidates of unwired sections are changed dynamically in this way as the wiring is proceeded, the wiring processing in compliance with the wire length instructed by the logic designer is executed at a high speed, the manual embedding time attended with the improvement of the wire rate is reduced and the computer system performance is improved.
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