发明名称 MEMORY ACCESS SHARED CONTROL SYSTEM
摘要 PURPOSE:To eliminate the need of extending a DMAC by sending an access permitting signal to an input/output device when the DMAC does not set flag information through control information set in an information setting part by a data signal and a data write clock signal from a processor. CONSTITUTION:A write clock signal A and the data signal are sent to an F/F part 17 from a processor 1. Meanwhile, an access request signal D is sent to a D/R part 13 from an input/output device 3 through an I/O adapter 7. Gate parts 18 and 19 are opened by signals D and A and a signal C issued from the F/F part 17. The signal D is inputted to a DMAC 5 through the gate part 18, and an arbitrating subroutine 20 checks a flag setting part 21; and if the flag is not set, the access permitting signal is outputted and is sent to the adapter 7 through the gate part 19 to permit an input/output device 3 to access a main storage part 2.
申请公布号 JPS62202253(A) 申请公布日期 1987.09.05
申请号 JP19860022322 申请日期 1986.02.04
申请人 FUJITSU LTD 发明人 TANAKA TAKAO
分类号 G06F13/28;(IPC1-7):G06F13/28 主分类号 G06F13/28
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