发明名称 INTEGRATED CIRCUIT
摘要 PURPOSE:To manufacture the integrated circuit without raising the noise of power supply system and lowering the input level margin when the output signals from multiple output buffers transit simultaneously by a method wherein delay elements differentiating the timing of outputting signals are juxtaposed between front and rear positions of multiple output buffers. CONSTITUTION:When the output signals from three state buffers 11-14 controlled by a control signal 2 transit simultaneously, the signals outputted from the three state buffers 11-14 respectively arrive at an output buffer 1031 in the delay time of zero, at another buffer 1032 through a delay element 1041 in the delay time of tau, at the other output buffer 1033 through delay elements 1042, 1043 in the delay time of 2tau likewise at the other output buffer 1034 through the other delay elements 1044-1046 in the delay time of 3tau. Through these procedures, the output signals S1-S4 from output buffers 1031-1034 transit respectively at the delay time of tau. Resultantly, the noise of power supply system made by the output buffers 1031-1034 is equivalent to the noise made by one each of transitting output buffer. Furthermore, the fluctuation in output signals S1-S4 can be reduced.
申请公布号 JPS62200745(A) 申请公布日期 1987.09.04
申请号 JP19860041915 申请日期 1986.02.28
申请人 TOSHIBA CORP 发明人 TAKATSUKI EIICHIRO
分类号 H01L21/82;H01L21/822;H01L27/04;H01L27/118 主分类号 H01L21/82
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