| 摘要 |
PURPOSE:To output an output of a shift register after shift operation as a data of final bit by providing plural shift registers of (n+1)-bit where the final bit data is fixed, and an OR circuit ORing outputs of the plural shift registers. CONSTITUTION:Shift registers 1a, 2a are shifted up to the (n+1)th bit set with a fixed value in the shift registers 1a, 2a to which n-bit parallel data is loaded and the OR circuit 5 is provided to an output stage of the shift registers 1a, 2a. Thus, the n-bit parallel data is loaded to the shift register 1a and the data is shifted up to the (n+1)th bit, the final output is the fixed value of the (n+1)th bit, '0'. After the output of the n-th bit of the shift register 1a, even when the load/shift of the parallel data is started, since the output of the shift register 1a is '0', only the output of the shift register 2a is outputted from the OR circuit 5. |
