发明名称 MULTIPLIER CIRCUIT
摘要 PURPOSE:To obtain a multiplier circuit that can perform the multiplication including corrections at a high speed by carrying out a correcting process at a high speed to convert an answer delivered in a pure binary number into a binary coded decimal number BCD. CONSTITUTION:A ROM 12 stores previously the pure binary numbers (0-81) in the form of decimal numbers as well as a pair of the quotient and the residue obtained by dividing the pure binary number by 10. Then the ROM 12 delivers both the quotient and residue corresponding to the result of multiplication of a multiplier 11 supplied as the address input data in the form of the 4-bit data respectively. Here the input/output data, etc. of the ROM 12 are weighted by the BCD codes. The 4-bit data outputted from the ROM 12 in terms of the quotient and the residue are supplied to an output data setting circuit 13. The circuit 13 outputs the result of the BCD type multiplication as shown by a format in the figure based on the data on those quotient and residue of 8 bits in all received from the ROM 12.
申请公布号 JPS62197824(A) 申请公布日期 1987.09.01
申请号 JP19860040703 申请日期 1986.02.26
申请人 TOSHIBA CORP 发明人 TOKUMARU TAKEJI
分类号 G06F7/38;G06F7/496;G06F7/52 主分类号 G06F7/38
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