| 摘要 |
PURPOSE:To obtain a semiconductor memory with a bipolar transistor, the degree of integration thereof is improved, by constituting a common electrode for a load resistor connected to the bipolar transistor and a Schottky barrier diode of a metallic silicide layer and a metallic electrode. CONSTITUTION:An N<+> type buried layer 2 and an N<-> type epitaxial layer 3 are formed to a P-type silicon substrate 1, and a bipolar transistor with a base region 5, an emitter region 6A for holding a memory and an emitter region 6B for writing the memory and a resistance region 8 directly connected to the base region 5 and a metallic silicide layer 9 are shaped to the N<-> type epitaxial layer 3. The side surface of the resistance region 8 is joined with the side surface of the metallic silicide layer 9 forming an SB diode in an ohmic manner. A common electrode 10 for the resistance region 8 and the SB diode is constituted of the metallic silicide layer 9 and a metallic electrode 7 shaped to the upper section of the layer 9. Accordingly, a unit memory cell can be scaled down. |
