| 摘要 |
PURPOSE:To match the output level with the standards and to quicken the operation of the titled circuit by providing a capacitor using a level shift resistor so as to clamp a base of an output bipolar transistor (TR) and neutralizing the stored electric charge in the base. CONSTITUTION:A CMOS level signal is inputted to the 1st inverters M1, M2 whose threshold value is set to the center of the CMOS level at the point side and to the center of the ECL level at the output side depending on the gate width of a MOS, clamped by a diode D1 and outputted to a load resistor R3 biased by a power supply VTT by using an output stage bipolar TR Q1 as the ECL output. A parallel circuit comprising a current control resistor R1 and a speed up capacitor C1 is inserted between the source and ground of a NMOS M2 to quicken the switching operation. Further, the base of the TR Q1 is clamped by using the diode D1 and a level shift register R2 to match the low level to the reference. |
