| 摘要 |
PURPOSE:To prevent the trouble caused from a lead-out phenomenon through the use of a clock signal with one phase by connecting the output terminal, the inverse of Q, of a flip flop D at a preceding stage to the input terminal D of the flip flop D. CONSTITUTION:The inverses of the output signals Q'A and Q'C ofthe 1st and 3rd staged D-F/Fs 11A and 11C to which a clock signal with a normal phase inputs, and the inverses of the output signals Q'B and Q'D of the 2nd and fourth staged D-F/Fs 11A and 11D to which a clock signal with an inverse phase inputs are initialized to a logic '1', and a logic '0', respectively. If under this state a data signal D to input the input terminal D of the F/F 11A is changed to a logic '1', the inverses of the signals Q'A-Q'D sequentially change in synchronization with a signal C after its 1/2 period. Accordingly the F/F11, directly exchanging signals, operates in synchronization with the signals C with normal and inverse phases, whereby no trouble such as leak-out phenomenon occurs irrespective of the values of electrical specification such as the holding time. |
