发明名称 SHIFT REGISTER
摘要 PURPOSE:To quickly drive a large capacity load by low power consumption by constituting such that each output of a dynamic type comparator is given to a buffer and its output is linked to a latch circuit. CONSTITUTION:The 1st clock phi1 fetches an input to the dynamic type comparator C, while the 2nd clock phi2 secures its output. However, since the comparator is of a dynamic type, a conducting current is not conducted. Afterward, the 3rd clock phi3 drives the buffer B to amplify the output of the comparator C. Thus the comparator and amplification are made individually, whereby the large capacity load can be quickly driven, and a quick action can be obtained in spite of low power consumption. As the output is provided with a latch circuit, the output is connected to a power source voltage or a grounding potential in a low impedance state even if the clock phi3 comes to a low level, and therefore the output holding time has no limit.
申请公布号 JPS62192098(A) 申请公布日期 1987.08.22
申请号 JP19860034673 申请日期 1986.02.18
申请人 MATSUSHITA ELECTRONICS CORP 发明人 NISHIMOTO TOSHIO;KAWAI HIDEKI;FUJII MASARU;OTA KIYOTO
分类号 G11C19/28;G11C7/10;G11C19/00 主分类号 G11C19/28
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