| 摘要 |
<p>PURPOSE:To reduce the area of a chip by providing a switching means which connects an output means to the output node of an address decoder that is fixedly associated with said output means while a switching command signal is outputted. CONSTITUTION:When a low voltage at +5V, for instance, is impressed on an input terminal A12, a level detector 14 outputs a normal read mode signal. As a result the address decoder 12 decodes an address signal supplied from the outside to select a memory cell, reads information in the selected memory cell to an I/O buffer 13, and outputs it to an external device through output terminals O0-O7. Namely, a switching transfer gate 15 connects the buffer 13 to an output terminal group 16. Next, when an input voltage of +12V at a high level is impressed on the terminal A12, the detector 14 outputs the switching command signal. As a result the gate 16 connects each output node of the decoder 12 to the terminal group 16.</p> |
