发明名称 TIMING EXTRACTION CIRCUIT
摘要 <p>PURPOSE:To make the pulse period constant by providing a flip-flop set by a CMI signal and reset by the output of a delay circuit and a band pass filter inputting the output of the flip-flop and extracting 1/T component of a CMI signal. CONSTITUTION:The flip-flop 1 having a set terminal and a reset terminal, the delay circuit 2 retarding a signal by a time 1/2f0 and the band pass filter 3 having a center frequency f0 are provided, Since the CMI code where a pulse is located at the latter half of a time slot as a '0' code is inputted, the set/reset terminal of the flip-flop 1 is operated at the trailing of the pulse. The input signal pulse En is subjected to level inversion from an H to an L level between time slots only, the flip-flop is set at that time and the pulse is led. After the time for a half time slot elapses, reset is applied by a signal En', the pulse is descended and a signal Fn including an f0 component appears at the output, the sinusoidal wave of the frequency f0 is obtained by giving the signal to the band pass filter 3.</p>
申请公布号 JPS62188445(A) 申请公布日期 1987.08.18
申请号 JP19860030070 申请日期 1986.02.13
申请人 NEC CORP 发明人 RIKIYAMA HIROKI
分类号 H04L7/00;H04L7/02;H04L7/027 主分类号 H04L7/00
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