| 摘要 |
PURPOSE:To prevent the rewrite of an internal data due to an induced noise, etc., in the holding period of a low power source voltage data, and to reduce the number of out-fitting parts, by providing a read mode fixing circuit which fixes a read/write signal at a level on the read side. CONSTITUTION:When a chip select signal, the inverse of CS, is in a standby state of high level with a read/write signal input circuit 1, a read/write signal R/W is cut off with a signal, the inverse of CS' passed through an input/output control circuit 4. Meanwhile, while a power source voltage VCC drops, and is at a level below than a prescribed reference voltage VR, a low power source voltage signal VCL is outputted from a power source voltage detection circuit 3. A read mode fixing circuit 2, while the signal VCL is present, fixes the output of the circuit 1 at the level at the read side, and the input/output control circuit 4 controls the data not to be written on a memory circuit 5, thereby the rewrite due to the induced noise, etc., being prevented. |
