发明名称 CLOCK SIGNAL GENERATOR
摘要 <p>PURPOSE:To delete an elapsing fluctuation and to improve the stability by inputting a digital signal from an A/D converter to a prescribed step of a delay circuit, operating an output having a prescribed phase difference in an arithmetic circuit with respect thereto, deciding a polarity in a polarity detecting circuit and controlling a voltage control oscillator. CONSTITUTION:The pulse of a color video signal corresponding to a period of a color burst signal is outputted through an LPF 1 in a control circuit 2, inputted to a polarity detecting circuit 11, the output of the voltage control oscillator 4 is inputted as a clock signal by the A/D converter 3 to convert into the digital signal and inputted to the delay circuit consisting of registers 6, 7. Then, the difference of sample values of a certain sampling point and a sampling point after 1 clock is operated by a subtracter 8, and the difference of the sample values between the certain sampling point and a sampling point before 1 clock is operated by a subtracter 9, respectively. Then, the arithmetic result in an adder and subtracter 10 is inputted to the polarity detecting circuit 11 to decide the polarity, if it is negative, a positive direct current power source 14 is selected, if it is positive, a negative direct current power source 15 is selected, outputted from an analog switch 12 to control the voltage control oscillator 4 through an LPF 13. Thereby, the ability in the phase of the clock signal is improved.</p>
申请公布号 JPS62175094(A) 申请公布日期 1987.07.31
申请号 JP19860017552 申请日期 1986.01.28
申请人 ALPS ELECTRIC CO LTD 发明人 TSUKAMOTO AKITO
分类号 H04N9/44;H03L7/06;H03M1/12;H04N9/66;H04N11/04 主分类号 H04N9/44
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