发明名称 PATTERN DRAWING CONTROL CIRCUIT
摘要 PURPOSE:To improve pattern drawing performance and controller execution efficiency by providing a temporary memory which operates at faster speed than a pattern drawing memory and a data generator before the pattern drawing memory. CONSTITUTION:FIFO which constitutes a temporary memory 4 can operate without weight cycle because data are written into FIFO at high speed. Until a left half character pattern is written into a pattern drawing memory 9, it is possible to perform address calculation for right half data and also obtain a spare time (alpha). During the spare time (alpha), a controller 1 periodically monitors a flipflop 5, and if the content is at low level, executes the operation to set an address, read the right half character pattern from a character pattern memory 3 and write it into the temporary memory 4. While the right half character pattern is read by a data generator 6 and a pattern is drawn to a pattern drawing memory 9, post- and pretreatments of data are executed. As soon as the flipflop 5 outputs a low level signal, next character pattern can be transferred.
申请公布号 JPS62174161(A) 申请公布日期 1987.07.30
申请号 JP19860017476 申请日期 1986.01.29
申请人 NEC CORP 发明人 SHIRAKU YUTAKA
分类号 B41J2/49;B41J5/46 主分类号 B41J2/49
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