| 摘要 |
<p>Two A-D converters which provide different embodiments of the general successive rectification algorithm Vout = 2|Vin| - Vref. One stage of a synchronous parallel converter generally comprises a comparator (32), and an op amp (35) with Vin as an input to its inverting input, the noninverting input connected to ground, and the output being Vout, with a first capacitor (C1) bridging the inputs of the op amp, and a second capacitor (C2) of half the capacitance of the first capacitor feeding back from the output of the op amp to its noninverting input. Each stage's Vin is compared to ground to provide a bit of information. One stage of the continuous parallel converter comprises a complementary transistor pair (M1, M2) and three current mirrors (70, 75, 80). The transistor pair, a first current mirror (70) and a second current mirror (75) act as a rectifier. The third current mirror (80) acts to subtract Iref from the rectified amplified Vin, and has Vref as an input and an output connected to Iout. The Iout of one stage acts as the Iin to a second stage, and the stages are cascaded. The direction of flow of Iin to each stage provides bits of information.</p> |
