| 摘要 |
PURPOSE:To transfer synchronously data and to suppress increase of power consumption by providing the first and second capacitors, precharging the capacitors alternately and cutting off one capacitor from the power source and connecting to a bus while another capacitor is precharged. CONSTITUTION:When a clock signal CLK is in L level, MOS FET 38, 40 become on state, and MOS FET 37, 41 become off state, and a capacitor 391 is charged up by a power source VDD, and one electrode is connected to a bus 11. When the clock signal CLK becomes H level, MOS FET 37, 41 become on state and MOS FET 38, 40 become off state, and a capacitor 392 is charged up by the power source VDD. At his time, if there is no gate that discharges the bus 11, H level of the bus 11 is kept stably, and when there is a gate that discharges the bus 11, the bus 11 becomes L level. Accordingly, a circuit that can transfer data synchronously with rise and fall of the clock signal, and does not cause increase of power consumption can be obtained.
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