| 摘要 |
A digital signal decoding system comprises a terminal for receiving a digital signal through a transmission path, which digital signal is encoded so that an error in one bit can be corrected in each of code words which are constituted by adding check bits to information bits and is modulated according to a self clock modulation system, a circuit for obtaining a demodulated signal by demodulating the digital signal, a first circuit for generating an encoded data and a clock signal from the demodulated signal, a circuit for generating an error possibility data from an output of the first circuit, which error possibility data assumes a first logic value at a bit position corresponding to a bit of the encoded data whereat an error does not exist and assumes a second logic value at a bit position corresponding to a bit of the encoded data whereat the possibility that an error exists is high, a memory circuit for pre-storing a first table containing the priority of a decoding sequence, and a circuit for obtaining the priority of the decoding sequence by referring to the first table based on the encoded data and the error possibility data and for obtaining a decoded data of an original data by correcting error in one or a plurality of bits of the encoded data and/or the error possibility data based on the priority.
|
