| 摘要 |
PURPOSE:To improve the efficiency of DMA transfer by controlling a DMA controller so that it transfers the data having the same bit width as that of a DMA transfer system at all times as soon as a DMA transfer request is supplied. CONSTITUTION:A hard disk controller (HDC) 9 request a system to perform the DMA transfer of data of an 8-bit unit. When the 1st DMA transfer request signal is outputted to a control circuit 2 from the HDC 9, the circuit 2 delivers a request signal to a block 1. Based on said request signal, the data equivalent to 8 bits fetched by a DMA controller from a memory 4 are transferred to the HDC 9. At the same time, the data of 8 bits fetched by the DMA controller from a memory 3 are held by a latch 5. Then the data held by the latch 5 are transferred to the HDC 9 to reset the system to its initial state by the next request signal. This process is repeated for DMA transfer. |
