| 摘要 |
PURPOSE:To prevent a latchup and an erroneous operation or damage due to the latchup without applying a voltage except a predetermined voltage to input/output pads by forming an input/output protecting circuit so as not to implant holes to a substrate. CONSTITUTION:An input protecting circuit of NPN transistor TR13 and a PNP TR14 is provided between the input pad 11 of a CMOS semiconductor device having N-type or P-type substrate and the node A of the input stage of an internal circuit 12. The node A is connected with the emitters of the TR13, TR14, potentials VSS, VCC of the TR13, TR14 are connected with the bases of the TR13, TR14, and potentials VCC, VSS are connected with the collectors. An output protecting circuit of NPN TR33 and PNP TR34 is provided between an output circuit 42 for amplifying the output of the internal circuit 32 and an output pad 31. The base regions of the TR13, 14 and 33, 34 of the protecting circuit are formed in well structure so that voltages except the potentials VSS, VCC are not applied to the input pad 11 and the output pad 31. |
