| 摘要 |
<p>PURPOSE:To speed up the operation by detecting an edge of an internal write signal so as to generate a series of timing signal to read an internal circuit. CONSTITUTION:Timing signals phisas, phisac required for the operation of a sense amplifier sent from a control circuit CONT are not generated at the write mode. A pulse generating circuit PG generates an output signal phi synchronously with a back edge when an internal write signal we goes from L to H attended with the end of write. The circuit CONT receives the signal phi to connect an input terminal of the sense amplifier SA to a common data line CD, a precharge signal phip is generated to precharge the line CD to a reference voltage. Thus, the circuit SA is brought into the operating state and an output of the amplifier SA is sent to a data output buffer DOB. After the amplifier is inactivated by the L level of the signals phisac, phisas, when the output enable signal OE is brought into an L level, the output signal of the buffer DOB is sent immediately from an I/O.</p> |
