| 摘要 |
PURPOSE:To minimize a circuit scale and to execute the highly speedy processing by normalizing a pass metric and a threshold. CONSTITUTION:The decoder is provided with the first adder 1 to add the previous pass metric from a pass metric register 7 and a threshold DELTA, a subtractor 2 to subtract a backward branch metric from the pass metric, the second adder 3 to add the pass metric and a forward branch metric, a calculating part 4 to modulo-calculate the output of the second adder 3 at the increase and decrease width DELTA of the threshold, a selector 5, and a pass deciding part 6 to control the selector 5 by the output of the subtracter 2 or the second adder 3. By the selector 5, the pass metric from the pass metric register 7, the output of the first and second adders 1 and 3, the output the subtracter 2 and the output of the calculating part 4 are selected, and added to a pass metric register 6 as the present pass metric.
|
