发明名称 |
DECODER CIRCUIT |
摘要 |
PURPOSE:To reduce input amplitude without saturating a transistor and to attain a high-speed operation of a decoder circuit, by shifting the level of the base voltage of the transistor constituting an AND gate of a decoder circuit. CONSTITUTION:The base of an npn transistor TRQ2K is connected to a joint N2K between split load resistances R1K and R2K together with the emitter connected to the base N4K of a TRQIJK (J=1-m) constituting an AND gate respectively. Thus the voltage of a joint N2K functions to shift the voltage of the base N4K of the TRQIJK to the voltageof the collector N3K by the voltage drop caused between the base and the emitter of the TRQ2K so that the TRQIJK is not saturated at all times. Thus it is possible to reduce the split load resistance value and then the input amplitude of a decoder circuit together with the output amplitude kept at the prescribed value. This secures a high-speed operation of the decoder circuit.
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申请公布号 |
JPS62164294(A) |
申请公布日期 |
1987.07.20 |
申请号 |
JP19860004965 |
申请日期 |
1986.01.16 |
申请人 |
HITACHI LTD;HITACHI DEVICE ENG CO LTD |
发明人 |
MATSUMOTO MASAAKI;HONMA NORIYUKI;NAKAMURA TORU;TANI KAZUHIKO |
分类号 |
G11C11/413;G11C11/34;H03M7/00 |
主分类号 |
G11C11/413 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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