| 摘要 |
PURPOSE:To improve manufacturing yield rate and to decrease costs, in manufacturing a CMOS type IC using self-alignment processes, by forming one conductivity type source and drain regions without using masks such as photoresist in two complementary MOS transistors. CONSTITUTION:On gate insulating films 16A and 16B, which are arranged on the surface of a semiconductor substrate 10, gate electrodes layer 18A and 18B comprising polysilicon are formed. Under the state where the opening parts 14A and 14B are not masked, e.g., arsenic ions are selectively implanted in the surface of the substrate, with the laminated parts of the gate insulating films 16A and 16B and the gate electrode layers 18A and 18B, the laminated part of the gate insulating film 16B and the gate electrode layer 18B and a field insulating film 14 is masks. N<+> type regions 20, 24, 22 and 26 for sources and drains are formed on one side and other side of each of the gate electrodes 18A and 18B, respectively. In the P-channel MOS transistor, P<+> source and drain regions are arranged and formed so as to erase the N<+> source and drain regions.
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