发明名称 CLOCK GENERATING CIRCUIT OF DATA PROCESSOR
摘要 <p>PURPOSE:To display an operation state accurately and speedily on an opponent device connected through a transmission line by outputting a clock signal only within a specific time after a clock generating circuit inputs a command signal. CONSTITUTION:The transmit clock generating circuit 2 when commanded again by a clock transmission command to send a transmit clock within a specific time of clock generation generates the transmit clock successively for the specific time. Consequently, the clock is sent out to the transmission line stably from a driver circuit 3. When the clock transmission is not recommanded within a certain time of the generation, it is judged that a data processor does not perform data processing, and the transmit clock generation is stopped at a certain time later. Consequently, the circuit 3 stops sending out the clock to the transmission line immediately after the stop of the transmit clock generation of the circuit 2 and the clock on the transmission line is ceased.</p>
申请公布号 JPS6061820(A) 申请公布日期 1985.04.09
申请号 JP19830168714 申请日期 1983.09.13
申请人 NIPPON DENKI KK 发明人 IDOKAWA ATSUSHI
分类号 H03K3/64;G06F1/04 主分类号 H03K3/64
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