| 摘要 |
A novel self diagnostic Cyclic Analysis Testing System (CATS) for functional testing of integrated circuit boards, and assemblies is disclosed, wherein a logic device under test is isolated and reconfigured to simulate a non-linear binary sequence generator which has known settings during normal fault free operation. The memory elements of the logic under test are preset to a known start setting, and the device is clocked for a given number of steps to define a testing cycle to operate the logic gates and memory elements of the device under test as the non-linear sequence generator. At the end of the testing cycle, the settings of the memory elements are compared with the known settings, and a fault condition is indicated when the setting(s) differ from the known setting.
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