发明名称 SYNCHRONIZING CIRCUIT FOR ASYNCHRONOUS INPUT
摘要 <p>PURPOSE:To prevent malfunction caused by a fact that an intermediate level is kept for a certain period of time or longer, by using a circuit which detects the internal intermediate level of a circuit and prevents a case where the intermediate level is kept for said period. CONSTITUTION:The inputs 24 and 25 of intermediate levels are inputted for a certain period of time or longer to a circuit consisting of a depression type transistor TR18, a capacitor 19, and enhancement type TRs 21 and 22. Thus an output 26 of a L level is outputted. The TR21 of the circuit 23 is turned on by the input 25 of an intermediate level. while the input 24 of an intermediate level is inputted to the TR22 through the TR18 and a RC delay circuit of the capacitor 19. then the TR22 is turned on when a certain period of time passed after the TR21 is turned on. Therefore, the output 26 is delivered only when both inputs 24 and 25 are supplied for a certain period or longer. Then the output 26 is delivered if the points of 3AND-NOR 13 and a 2AND-NOR 14 are kept an intermediate levels for a certain period of time or longer. Thus the output of the NOR 14 is set at an L level with the output of the NOR 13 set at an H level respectively. Then both outputs can be free from intermediate levels.</p>
申请公布号 JPS62152058(A) 申请公布日期 1987.07.07
申请号 JP19850294158 申请日期 1985.12.26
申请人 NEC CORP 发明人 HIRASAWA MASAO;OURA TOSHIO
分类号 G06F13/42;G06F1/04;G06F1/12 主分类号 G06F13/42
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