发明名称 'AND' CIRCUIT
摘要 PURPOSE:To obtain an 'and' circuit where the mutual division between inputs is separated in a direct current way by turning on and off respective transistors in accordance with a clock pulse and by extracting this with a linking means only when the first and second logical input signals are respectively and simultaneously impressed. CONSTITUTION:To an input IN, a clock pulse CK of the frequency sufficiently higher than the changing period of respective logical input signals is given, the light emitting diode of a photocoupler 1 used as the first light emitting element and light receiving element is driven by the clock pulse CK and emits the light intermittently in accordance with this. When an input terminal A1 is a positive pole, the same terminal G1 is a negative pole and as the electric power source to these, the first logical input signal is impressed, a transistor Q1 is turned on and off. To the collector of the transistor Q1, a PC2 is inserted as the second light emitting element and light receiving element, to the division between input terminals A2 and G2, the second logical input signal is impressed, a transistor Q2 at the next stage is turned on and off. In the same way, (n) stages are connected and from the optional output, an 'and' output signal is obtained.
申请公布号 JPS62152221(A) 申请公布日期 1987.07.07
申请号 JP19850292095 申请日期 1985.12.26
申请人 KYOSAN ELECTRIC MFG CO LTD 发明人 ENOMOTO TAKASHI
分类号 H03K19/007;H03K19/20 主分类号 H03K19/007
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