发明名称 Soft-limited digital pulse compressor
摘要 A circuit is provided for correlating both the phase and amplitude of received radar signals with the phase of a transmitted binary reference phase code, which enables implementation by off-the-shelf hardware. The received signal is demodulated and quadrature detected, and each segment of small duration of the received signal is converted to a three-bit data code word, with each data word defining both the phase and the amplitude of the demodulated received signal. Each bit of the same significance (e.g., most significant bit or least significant bit) of a series of data words is delivered to a different one of a group of one-bit correlators. Each correlator correlates the series of bits of the same significance from a sequence of data words, with the bits of the binary reference phase code. The outputs of the correlators whose bits represent the amplitude of the received signal, are multiplied according to the significance or position of the bit, and the products are added.
申请公布号 US4679210(A) 申请公布日期 1987.07.07
申请号 US19850756480 申请日期 1985.07.18
申请人 ITT GILFILLAN, A DIVISION OF ITT CORPORATION 发明人 RATHI, DEVDAS D.
分类号 G01S13/28;H03M7/30;(IPC1-7):G06F15/34 主分类号 G01S13/28
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