| 摘要 |
To reduce the parasitic capacitance due to the graft base area in a transistor device and to miniaturize the device, the graft base area is connected to a conductive layer to be connected to the base electrode through a minute gap of about 1,000 ANGSTROM . This minute gap can be formed by leaving an oxide resistant layer (1,000 ANGSTROM ) at the side wall portion of the conductive layer of which peripheral portion is perpendicular to the surface of the base area by applying an isotropic etching technique and by removing the remaining oxide resistant layer on the basis of selective etching technique, after thermal oxidation of the device with masking the side wall portion by the remaining oxide resistant layer.
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