| 摘要 |
PURPOSE:To decrease a quantization-error of phase as for as possible and thereby to make the titled circuit similar to an analog synchronizing circuit by generating plural clocks whose phases are delayed in order from an original clock within the period of one clocking, and stopping and restarting the supplying of clock to a counter by means of an internal signal and an external signal. CONSTITUTION:When one cycle of a horizontal synchronization ends and an internal horizontal synchronizing signal HS is generated, a signal F falls, and later, when a clock C rises, a flip-flop 54b fetches it and a Q-output turns to L and H respectively, and further an AND gate 56b is closed to stop the transmission of the clock C and to release the cleaning of other flip-flops. The restarting of the said transmission of the clock C is executed when the signal F turns to H and an input clock rises continually. At this time, a clock which is selected at this time is such one that rises the earliest after the rising of the signal F. Thereafter, the above mentioned process is repeated, and the external synchronization and the internal synchronization are made aligned in phase maximally possible.
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