发明名称 PEAK VALUE DETECTION CIRCUIT
摘要 PURPOSE:To suppress the peak value detection error due to the fluctuation of a mark rate by providing a negative feedback path comprising the mark rate detection circuit between a gain variable amplifier and an amplitude limit circuit provided at the post stage. CONSTITUTION:An output of a variable gain amplifier 1 is divided into two; the one is given to a peak detection circuit 2, where the peak value is detected and fed to a comparison circuit 3 and the other is given to an amplitude limit circuit 4, where the value is waveform-shaped to a constant amplitude and the mark rate is detected by a mark rate detection circuit 5. The detected mark rate information is inputted to an inverting input being the other input of the comparison circuit 3, where the output of the mark rate detection circuit 5 is used as a comparison reference value to compare the said peak value. Since the variable gain amplifier 1 is controlled by the output of the comparator 3, the negative feedback of the mark rate information is applied to suppress the error of the peak value detection due to the fluctuation of the mark rate.
申请公布号 JPS62145909(A) 申请公布日期 1987.06.30
申请号 JP19850285538 申请日期 1985.12.20
申请人 HITACHI LTD;HITACHI CABLE LTD 发明人 KINOSHITA TAIZO;YAMASHITA KIICHI;GOTO MASAHIRO
分类号 H03G3/30;H03K5/02 主分类号 H03G3/30
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