| 摘要 |
PURPOSE:To make it possible to reduce latch-up and to implement high integration density and high performance, by providing both an MIS type nonvolatile memory element and a CMOS circuit. CONSTITUTION:On the surface region of a first isolated epitaxial layer 5, an n-channel type MNOS type nonvolatile memory transistor is formed. In this transistor, n-type diffused layers 8 and 9 are a source and a drain. A gate electrode 12 is provided on a silicon oxide film 10, which is a gate insulating film 10 and a silicon nitride film 11. On the surface region of an n-type well layer 7, a p-channel type MOS transistor is formed. In this transistor, p-type diffused layers 13 and 14 are a source and a drain respectively. A gate electrode 16 is provided on an gate insulating film 15 in this structure. |
