| 摘要 |
PURPOSE:To decrease the generation of a shock by executing stop of detection of a dummy signal, or initialization of either a write address or a read-out address of a storage device, when a read-out clock frequency is being controlled. CONSTITUTION:In a read/write address counter relative difference detecting circuit 22, a relative difference of a write address signal WA and a readout address signal RA is detected, and when it goes to a prescribed difference before the write address signal WA and the read-out address signal RA are superposed, a write address counter 16 and a read-out address counter 21 are initialized, and the generation of a long burst error can be evaded. In case a dummy flag bit is lost and a read-out clock frequency control cannot be executed, a dummy signal is written in a frame memory 17-1, and also, in case the read-out clock frequency control cannot be executed, in case of demodulation, shock noise is generated. In such a case, when a PN signal is applied as a dummy data, even if the dummy data is demodulated, the level goes to zero, the shock noise can be evaded.
|
