| 摘要 |
<p>PURPOSE:To make high-speed simulation processing in a software logical simulation, by making an event processing section which requires much processing time to hardware. CONSTITUTION:A simulation table 200 contains the logical information, information relating connection, state value information, and event time information of a circuit to be subjected to a logical simulation described in the unit of node. Moreover, a simulation time controlling mechanism 300 which controls simulation time, event extracting mechanism 400 which accurately investigates the event time information of the table 200 and extracts a node which meets the event time, and event arithmetic mechanism 500 which calculates an outputting condition from the logical information of the extracted node and input state value information are provided. Then control of each mechanism is performed by a control circuit 700 and, at the same time, a node which is calculated and whose outputting state varies is set to event time information as a future event by means of a registering mechanism 600.</p> |
