发明名称 CLOCK CIRCUIT SYNCHRONIZER
摘要 <p>Synchronization of a local timing signal with an incoming reference timing signal is realized by employing a frequency estimator and frequency synthesizer in conjunction with a local fixed oscillator. The frequency estimator includes a first phase-locked loop including an integrator for generating a frequency estimate which is the difference between the frequency of the incoming reference timing signal and the frequency of the fixed oscillator signal. The phase value of the frequency estimate obtained by integrating the frequency estimate is supplied to a second phase-locked loop which includes a digitally controlled oscillator to generate the local timing signal. If the incoming reference timing signal is lost or if there is too large a variation in a phase error signal in the first phase-locked loop, the value of the frequency estimate is held constant. Consequently, the second phase-locked loop never free runs and the local timing signal remains in synchronization with the reference timing signal.</p>
申请公布号 JPS62137936(A) 申请公布日期 1987.06.20
申请号 JP19860286085 申请日期 1986.12.02
申请人 AMERICAN TELEPH & TELEGR CO <ATT> 发明人 DOMINITSUKU SUKOODO
分类号 H04L7/033;H03L7/06;H03L7/07;H03L7/08;H03L7/14;H04J3/06;H04L7/00 主分类号 H04L7/033
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