| 摘要 |
<p>PURPOSE:To eliminate the need for a complicated control pulse generating circuit and to output an input data whose bits are replaced by selecting a low speed data at a desired position of a time interval of a high speed clock. CONSTITUTION:An input data whose transmission speed is M-bit/sec at an input terminal 10 is inputted and an output data whose transmission speed is N-bit/sec (N is a multiple of M) at an output terminal 11 is inputted as feedback. Then an input signal is selected by 1/Nsec being a data output time of 1-bit in a/Msec being a data input time in 1-bit and inputted to a shift register 1, an output signal is selected in other time and a selector 2 is controlled by a selection pulse input at a selection pulse input terminal 12 inputted again to a shift register 9, and the shift register 1 is operated by a high speed output clock at a clock input terminal 3. In controlling the pulse position of the selection pulse, the write timing in the shift register is adjusted and a high speed data whose bits are replaced is outputted.</p> |
